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TMCNet:  Mentor Graphics unveils design platform for Samsung's IC manufacturing process

[January 01, 2013]

Mentor Graphics unveils design platform for Samsung's IC manufacturing process

Jan 01, 2013 (Datamonitor via COMTEX) -- Mentor Graphics Corp., a supplier of electronic design automation, or EDA, tools - computer software and emulation hardware systems, has announced a comprehensive design, manufacturing, and post tapeout enabling support for Samsung's 14nm IC manufacturing processes, providing customers with a complete design-to-silicon flow concurrent with early process availability.
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The fully interoperable Mentor flow helps customers achieve fast design cycles and first time silicon success. The Mentor solutions optimized for Samsung's 14nm offerings include the Calibre platform with design rule checking (DRC), LVS checking, extraction, design for manufacturing (DFM) and advanced fill, as well as the Tessent design for test (DFT) suite and yield analysis tools.

"Samsung and Mentor have been working together to speed the enablement of design and manufacturing co-optimization for many years, and our collaboration is more important than ever at the 14nm node," said Dr Kyu-Myung Choi, senior vice president of System LSI infrastructure design center, Device Solutions, Samsung Electronics.

"The design rules for 14nm are extremely complex with the introduction of FinFETs in addition to double patterning (DP) layers. It is critical that physical design, verification and testing tools are intimately aligned with the manufacturing processes of the target foundry. Since Samsung also uses the Mentor Calibre solution for its own IC development, designers using it will get accurate and immediate feedback so they can co-optimize the design process." The Calibre platform creates decomposed double patterning (DP) layouts that are compliant with all of Samsung's 14nm lithography requirements and tuned to the Samsung mask synthesis and OPC process, which is also provided by Mentor at 14nm. It also provides designers with feedback on complex design rules for FinFETs, and specific coaching on elimination of DFM litho errors to make fixing violations faster and more accurate.

Calibre tools for LVS and extraction have been calibrated to ensure accurate device and parasitic models for Samsung FinFETs, eliminating 'double-counting' of important effects that can occur with other tools. Moreover, Calibre SmartFill ensures there are no CMP issues with designs by intelligently placing fill structures to achieve planarity while minimizing timing issues.

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